Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Tue Aug 30 2005 10:48 pm


Sean Kelly wrote:
[...]
> - all stores have release semantics
> - all loads have acquire semantics

"all" == "ordinary x86" (processor-consistent stuff).

> 
> So am I correct in concluding that, at a program level, loads and
> stores (from a single CPU) appear to occur in program order for all x86
> processors?  

Well, not quite. Under PC you may still need a store-load fence.

>             I suppose this would explain why the documentation for
> LOCK says nothing about its effect on memory ordering.

Locked stuff implies compound release+acquire (full fence)... but 
only for ordinary processor-consistent stuff.

"For the P6 family processors, locked operations serialize all 
 outstanding load and store operations (that is, wait for them 
 to complete). This rule is also true for the Pentium 4 and 
 Intel Xeon processors, with one exception: ***load operations 
 that reference weakly ordered memory types (such as the WC 
 memory type) may not be serialized.***"

regards,
alexander.

.