Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Sean Kelly
Date : Tue Aug 30 2005 01:25 pm

Alexander Terekhov wrote:
> David Hopwood wrote:
> [...]
> > Stores by each processor occur in program order, that's clear. You're saying
> > that stores made by processor 1 can nevertheless be loaded by processor 2
> > out of program order. I see that there could be memory models and
> > implementations for which this is possible, e.g. due to speculation.
> > But how is it consistent with saying that all loads have acquire semantics?
....
> For not weakened "ordinary" memory, the effects are not visible unless
> you sit on the "system bus" or care about discards.
....
> > Which is all fine, but if speculative loads have no effect on the memory
> > model, I still have no idea what the point of lfence is. Unless it is only
> > needed when the memory ordering is weakened using MTRRs etc.?
>
> That too.

All this talk of the system bus in Intel docs is misleading since
behavior isn't observable at that level without testing equipment.  But
from what you've said Alex, this seems apparent:

- all stores have release semantics
- all loads have acquire semantics

So am I correct in concluding that, at a program level, loads and
stores (from a single CPU) appear to occur in program order for all x86
processors?  I suppose this would explain why the documentation for
LOCK says nothing about its effect on memory ordering.


Sean

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