Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Aug 29 2005 11:15 pm


Joe Seigh wrote:
[...]
> You want sequential consistency, I think.

You mean "Performing a load Globally" ("A load is globally 
performed if it is performed and if the store that is the source 
of the returned value has been performed") and 

----
Conditions for Sequential Consistency

(A) before a load is allowed to perform with respect
to any other processor, all previous load accesses
must be globally performed and all previous store
accesses must be performed, and

(B) before a store is allowed to perform with respect
to any other processor, all previous load accesses
must be globally performed and all previous s tore
accesses must be performed.
----

Not really. The definition of performing a load globally is used 
neither for PC nor for RCpc.

PC is this:

----
Conditions for Processor Consistency

(A) before a load is allowed to perform with respect to 
any other processor, all previous load accesses must be 
performed, and

(B) before a store is allowed to perform with respect to 
any other processor, all previous accesses (loads and
stores) must be performed.
^^^^^^^^^^^^^^^^^^^^^^^^^

[...]

A load by Pi is considered performed at a point in time when the 
issuing of a store to the same address by any P cannot affect the 
value returned by the load. A store by Pi is considered performed 
with respect to Pk (i and k different) before a point in time 
when issuing a load to the same address by Pk returns the value 
defined by this store or a subsequent store to the same address 
that has been performed with respect to Pk. A store by Pi 
eventually performs with respect to Pi. If a load by Pi performs 
before the last store (in program order) to the same address by 
Pi performs with respect to Pi, then the load returns the value
defined by that store. Otherwise, the load returns the value 
defined by the last store to the same address (by any P) that 
performed with respect to Pi (before the load performs). A store 
                                                         ^^^^^^^
is performed when it is performed with respect to all processors.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
----

regards,
alexander.

.