Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 04:38 pm

Alexander Terekhov wrote:
> Joe Seigh wrote:
> [...]
> 
>>>>>http://research.compaq.com/wrl/people/kourosh/papers/1990-rc-isca.pdf
>>>>>http://research.compaq.com/wrl/people/kourosh/papers/1993-tr-68.pdf
>>>>
>>>>Same thing.
>>>>I do not think this "processor consistency" means what you think it means.
>>>
>>>
>>>Show me your proof for this processor consistency.
>>>
>>
>>I already did.  The store by processor B into Y is *after* the stores
>>into the object by processor A since they preceeded the store into
>>X by processor A.  But since the stores into the object are by processor
>>A and the store into Y is by processor, different processors, you can't
>>infer that you're read them in the order they were written as *explicitly*
>>stated by the definition for processor consistency.
> 
> 
> You mean as explicitly stated by definition in "2.2 Processor Consistency" 
> (1990-rc-isca.pdf) subject to "Extension to Dubois’ Abstraction" (1993-tr-
> 68.pdf) "Performing a Memory Request"? 
> 
> How so?
> 
Yes.  That doesn't affect the definition of processor consistency.  It's defining
what "Performaning a Memory Request" means, specifically with respect to a
single memory location.  It doesn't affect stores by different processors to
different memory locations.  You want sequential consistency, I think.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.