Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 04:04 pm

Peter Dimov wrote:
> Joe Seigh wrote:
>>I googled per Alexander's suggestion
>>http://www.cs.nmsu.edu/~pfeiffer/classes/573/notes/consistency.html
>>which defined it as thus
>>
>>  "Writes done by a single processor are received by all other processors
>>  in the order in which they were issued, but writes from different
>>  processors may be seen in a different order by different processors."
> 
> 
> Well, the x86 model (and SPARC TSO, IIUC) is stronger than that. I
> don't know of an architecture that implements the above kind of
> processor consistency.
> 
> x86 is the best compromise between programmability and performance. I
> doubt that it will go away or be replaced by a weaker model. All weaker
> models were killed by it.

Unless I'm implementing a synchronization primative, I usually use the
synchronization primatives which guaranteed correctness no matter what
the memory model (within reason, i.e. you can port to it).  I don't
think anyone thinks Posix is all that bad (as long as you don't compare
it to lock-free. :) ).  


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.