Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 03:57 pm

Alexander Terekhov wrote:
> Joe Seigh wrote:
> 
>>Alexander Terekhov wrote:
>>
>>>Joe Seigh wrote:
>>>[...]
>>>
>>>
>>>>I already proved processor consistency doesn't work the way you think
>>>>it does.
>>>
>>>
>>>http://research.compaq.com/wrl/people/kourosh/papers/1990-rc-isca.pdf
>>>http://research.compaq.com/wrl/people/kourosh/papers/1993-tr-68.pdf
>>
>>Same thing.
>>I do not think this "processor consistency" means what you think it means.
> 
> 
> Show me your proof for this processor consistency.
> 

I already did.  The store by processor B into Y is *after* the stores
into the object by processor A since they preceeded the store into
X by processor A.  But since the stores into the object are by processor
A and the store into Y is by processor, different processors, you can't
infer that you're read them in the order they were written as *explicitly*
stated by the definition for processor consistency.

Normal memory barriers infer order of accesses to memory so it doesn't
matter if different processors do the stores as long as you have
memory barriers in the right places.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.