Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Peter Dimov
Date : Mon Aug 29 2005 12:41 pm

Joe Seigh wrote:
> Peter Dimov wrote:

> > Processor consistency behaves "as if" there is system memory (cache is
> > transparent) and CPU's have store queues that can satisfy their own
> > loads.
> >
> > So CPUs #3..#N will see the same sequence if CPUs #1 and #2 perform
> > stores.
> >
> > Discrepancies in store order only appear because CPU #1 can observe its
> > own stores early.
> >
> > In your example, C will see the stores by A and B in order.
> >
> I googled per Alexander's suggestion
> http://www.cs.nmsu.edu/~pfeiffer/classes/573/notes/consistency.html
> which defined it as thus
>
>   "Writes done by a single processor are received by all other processors
>   in the order in which they were issued, but writes from different
>   processors may be seen in a different order by different processors."

Well, the x86 model (and SPARC TSO, IIUC) is stronger than that. I
don't know of an architecture that implements the above kind of
processor consistency.

x86 is the best compromise between programmability and performance. I
doubt that it will go away or be replaced by a weaker model. All weaker
models were killed by it.

Under the x86 model, if A writes X and B writes Y, processors C-F will
all see the same sequence of writes, X,Y (without loss of generality).
However B can observe Y,X. So the above definition does describe x86,
just not in its entirety.

.