Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 02:13 pm

David Hopwood wrote:
> Alexander Terekhov wrote:
> 
>> Joe Seigh wrote:
>> [...]
>>
>>> The official memory model states otherwise so you probably shouldn't
>>> use the term "memory model" that way.  You mean load ordering as
>>> implemented.  It's not clear whether you're talking about processor
>>> order or memory order here.  
>>
>>
>> In Intel speak, "memory order[ing]" is "the order in which the 
>> processor issues reads (loads) and writes (stores) through the system 
>> bus to system memory." (7.2. MEMORY ORDERING).
> 
> 
> *Oh*. Now I understand why their documentation doesn't make sense.
> They're taking an aspect of the implementation and calling it a memory
> model.
> 

If I understand it correctly, the speculative loads aren't observable by
programs using normal memory.  You'd need a scope on the system bus to
notice them.  If loads are indeed in order then they shouldn't have
mentioned the phrase speculative or out-of-order w.r.t. loads.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.