Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 01:58 pm

Peter Dimov wrote:
> Joe Seigh wrote:
> 
> 
>>the reads would have to be invalidated if *any* memory accesses by *any*
>>processor were observed on the system bus before any prior reads completed.
> 
> 
> I don't see why. Only stores affecting the speculatively carried loads
> will invalidate. If CPU #1 reads X, Y and Z out of order and CPU #2
> writes to W, there is no reason to discard the values of X, Y and Z.
> 
Possibly.  I was thinking of mixes of loads and stores but that would
probably require explicit load/store and store/load members which may
moot the whole issue.  I wouldn't say it was safe without giving it
a bit of thought first.

-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.