Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Aug 29 2005 07:51 pm


David Hopwood wrote:
[...]
> Is then <http://gee.cs.oswego.edu/dl/jmm/cookbook.html> incorrect when
> it says that SPO requires lfence to implement a LoadLoad barrier?

Ha!

< Forward Inline >

-------- Original Message --------
Message-ID: <e52efbe105062109243268fbc2@mail.gmail.com>
Date: Tue, 21 Jun 2005 18:24:31 +0200
From: Alexander Terekhov <snip>
To: Doug Lea <snip>
Subject: "Speculative Processor Ordering"

G'Day,

http://gee.cs.oswego.edu/dl/jmm/cookbook.html

----
x86-SPO=20
Allegedly upcoming Intel x86, AMD Opteron, and possibly others. Intel
calls consistency properties for these "Speculative Processor
Ordering" (SPO). (As of this writing, no existing x86 or x86-64
processors are known to be SPO. All are PO.) See above, plus AMD
x86-64 Architecture Programmer's Manual Volume 2: System Programming
----

I allege that with respect to ordinary (not-weakened, non-SSE-stuff, etc.)=
=20
memory visibility,  x86-SPO is nothing but classic processor consistency=20
(same as x86-PO).

The (ugly) specs simply try to explain implementation behavior to the obser=
ver=20
sitting on the "System Bus", not the memory model (which is is processor=20
consistency) as seen by the program (i.e. apart from the activities seen on=
 =20
that "System Bus" thingy).

IOW, "LoadLoad" is implied (as far as JMM is concerned) on both x86-PO=20
x86-SPO, and lfence can be safely omitted as long you don't care what=20
happens/can be observed on the "System Bus".

Now please prove me wrong. ;-)

TIA.

regards,
alexander.

.