Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Aug 29 2005 07:43 pm


Joe Seigh wrote:
> 
> Sean Kelly wrote:
> > Joe Seigh wrote:
> >
> >>If you're thinking that doesn't matter because processor consistency
> >>gives you release and acquire semantics between two processors.  But
> >>what if you have 3 (or more) processors?   For example, processor A
> >>initializes and stores its address in X.   Processors B reads X.  So
> >>far, so good.  All the stores by A are read in proper order by B.
> >>Now processors B stores the object address in Y and processor C reads Y.
> >>Now there's a problem.  There's no guarantee that processor C will see
> >>the writes by A in proper order (i.e. relative to the read of Y).  So
> >>processor consistency doesn't give you acquire and release as they are
> >>commonly understood.
> >
> >
> > So assuming this were the case, how would memory ordering be achieved
> > on Intel/AMD?  The instruction set has precious few (ie. no)
> > instructions to achieve this.
> 
> Any of the serializing instructions, e.g. cpuid, lock, etc....  Linux
> uses a dummy XCHG agains the stack (implied LOCK).  The xFENCE are offered
> as being more efficient since all they basically do is serialize and not
> do something else as well.             ^^^^^^^^^^^^^^^^^^^^^^^^^

Serialize what? (cpuid aside for a moment.) Chapter and verse please.

Please show some pseudo code with *FENCE that you think is needed to
ensure visibility of data published by A in X to C after republishing 
it in Y by B.

I think you've been googling too much. ;-)

regards,
alexander.

.