Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : David Hopwood
Date : Mon Aug 29 2005 05:35 pm

Alexander Terekhov wrote:
> Joe Seigh wrote:
> [...]
> 
>>The official memory model states otherwise so you probably shouldn't
>>use the term "memory model" that way.  You mean load ordering as
>>implemented.  It's not clear whether you're talking about processor
>>order or memory order here.  
> 
> In Intel speak, "memory order[ing]" is "the order in which the 
> processor issues reads (loads) and writes (stores) through the system 
> bus to system memory." (7.2. MEMORY ORDERING).

*Oh*. Now I understand why their documentation doesn't make sense.
They're taking an aspect of the implementation and calling it a memory
model.

> Weakened memory and SSE 
> stuff aside for a moment, the *memory model* is processor consistency 
> (aka processor ordering in Intel speak) with all loads having acquire 
> semantics. SPO (Speculative Processor Ordering) implementation doesn't 
> [break] it. End of story.

Is then <http://gee.cs.oswego.edu/dl/jmm/cookbook.html> incorrect when
it says that SPO requires lfence to implement a LoadLoad barrier?

-- 
David Hopwood <david.nospam.hopwood@blueyonder.co.uk>

.