Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Peter Dimov
Date : Mon Aug 29 2005 10:32 am

Joe Seigh wrote:

> If you're thinking that doesn't matter because processor consistency
> gives you release and acquire semantics between two processors.  But
> what if you have 3 (or more) processors?   For example, processor A
> initializes and stores its address in X.   Processors B reads X.  So
> far, so good.  All the stores by A are read in proper order by B.
> Now processors B stores the object address in Y and processor C reads Y.
> Now there's a problem.  There's no guarantee that processor C will see
> the writes by A in proper order (i.e. relative to the read of Y).  So
> processor consistency doesn't give you acquire and release as they are
> commonly understood.

Processor consistency behaves "as if" there is system memory (cache is
transparent) and CPU's have store queues that can satisfy their own
loads.

So CPUs #3..#N will see the same sequence if CPUs #1 and #2 perform
stores.

Discrepancies in store order only appear because CPU #1 can observe its
own stores early.

In your example, C will see the stores by A and B in order.

.