Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Peter Dimov
Date : Mon Aug 29 2005 10:21 am

Joe Seigh wrote:

> If you had a memory model that states reads were in order (ala sparc TSO) and
> under the cover allowed out of order speculative reads, ...

That's the x86 memory model.

> the reads would have to be invalidated if *any* memory accesses by *any*
> processor were observed on the system bus before any prior reads completed.

I don't see why. Only stores affecting the speculatively carried loads
will invalidate. If CPU #1 reads X, Y and Z out of order and CPU #2
writes to W, there is no reason to discard the values of X, Y and Z.

.