Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Sean Kelly
Date : Mon Aug 29 2005 09:33 am

Joe Seigh wrote:
>
> If you're thinking that doesn't matter because processor consistency
> gives you release and acquire semantics between two processors.  But
> what if you have 3 (or more) processors?   For example, processor A
> initializes and stores its address in X.   Processors B reads X.  So
> far, so good.  All the stores by A are read in proper order by B.
> Now processors B stores the object address in Y and processor C reads Y.
> Now there's a problem.  There's no guarantee that processor C will see
> the writes by A in proper order (i.e. relative to the read of Y).  So
> processor consistency doesn't give you acquire and release as they are
> commonly understood.

So assuming this were the case, how would memory ordering be achieved
on Intel/AMD?  The instruction set has precious few (ie. no)
instructions to achieve this.

> And you *really* do need to read the AMD docs.

I've got them but have been preferring the Intel docs as they're a bit
more readable.  I assume this is in the section on the memory model?


Sean

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