Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 12:17 pm

Alexander Terekhov wrote:
> Joe Seigh wrote:
> [...]
> 
>>>http://groups.google.de/group/comp.lang.c++.moderated/msg/40e6f068496500a7
>>>("If you think it through, you will see..."
>>>
>>
>>It's not clear at all.  Processor consistency is a totally meaningless term
>>to use for a multiprocessor memory model.
> 
> 
> Processor consistency is the term of the art for multiprocessor *memory 
> model*.
> 
> Go google it.

I was thinking of processor logical order but it doesn't matter.  It may
be useful for building HPC clusters but it's useless for  SMMP (shared
memory multi-processing).   That's because shared memory is the arbiter
in synchronization.  I.e. it's the order of reads and writes to memory
that count, not the order by specific processors.  Processors consistency
even explicitly states stores by different processors aren't necessarily
read in the order they appear in memory.

If you're thinking that doesn't matter because processor consistency
gives you release and acquire semantics between two processors.  But
what if you have 3 (or more) processors?   For example, processor A
initializes and stores its address in X.   Processors B reads X.  So
far, so good.  All the stores by A are read in proper order by B.
Now processors B stores the object address in Y and processor C reads Y.
Now there's a problem.  There's no guarantee that processor C will see
the writes by A in proper order (i.e. relative to the read of Y).  So
processor consistency doesn't give you acquire and release as they are
commonly understood.

[...]
> 
> Got it now?

And you *really* do need to read the AMD docs.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.