Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Aug 29 2005 03:48 pm


Joe Seigh wrote:
[...]
> > http://groups.google.de/group/comp.lang.c++.moderated/msg/40e6f068496500a7
> > ("If you think it through, you will see..."
> >
> 
> It's not clear at all.  Processor consistency is a totally meaningless term
> to use for a multiprocessor memory model.

Processor consistency is the term of the art for multiprocessor *memory 
model*.

Go google it. 

And, BTW, regarding the term "memory model":

http://rsim.cs.uiuc.edu/~sadve/jmm/sc-.pdf

"The memory model is the interface between the system and the programmer 
 that defines the values that a read in a program is allowed to return."

As for SSE fencing...

ftp://download.intel.com/design/Pentium4/manuals/25366516.pdf

----
In general, ***WC semantics*** require software to ensure coherence, 
with respect to other processors and other system agents (such as 
graphics cards). Appropriate use of synchronization and fencing must 
be performed for producer-consumer usage models.

[...]

The SFENCE (store fence) instruction provides greater control over 
the ordering of store operations when using ***weakly-ordered*** 
memory types.

[...]

The SFENCE (Store Fence) instruction controls write ordering by 
creating a fence for memory store operations. This instruction 
guarantees that the result of every store instruction that precedes 
the store fence in program order is globally visible before any 
store instruction that follows the fence. The SFENCE instruction 
provides an efficient way of ensuring ordering between procedures 
that produce ***weakly-ordered*** data and procedures that consume 
that data.

[...]

SSE2 extensions introduce two new fence instructions (LFENCE and 
MFENCE) as companions to the SFENCE instruction introduced with SSE 
extensions.

The LFENCE instruction establishes a memory fence for loads. It 
guarantees ordering between two loads and prevents speculative loads 
from passing the load fence (that is, no speculative loads are allowed 
until all loads specified before the load fence have been 
carried out).

The MFENCE instruction combines the functions of LFENCE and SFENCE by 
establishing a memory fence for both loads and stores. It guarantees 
that all loads and stores specified before the fence are globally 
observable prior to any loads or stores being carried out after the 
fence.
----

So part from the store-load fencing provided by mfence, SSE fence
instructions has really nothing to do with "ordinary" memory under
processor consistency memory model (load:acquire, store:release,
and locked-stuff:release+acquire).

Got it now?

regards,
alexander.

.