Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Mon Aug 29 2005 09:40 am

Alexander Terekhov wrote:
> Joe Seigh wrote:
> [...]
> 
>>        "1. Reads can be carried out speculatively and in any order."
> 
> 
> http://groups.google.de/group/comp.lang.c++.moderated/msg/40e6f068496500a7
> ("If you think it through, you will see..."
> 

It's not clear at all.  Processor consistency is a totally meaningless term
to use for a multiprocessor memory model.  

The above statement can be rewritten as

     1. Reads can be carried out speculatively.
     2. Reads can be carried out in any order.

You seem to be reading it as something else.

If you had a memory model that states reads were in order (ala sparc TSO) and
under the cover allowed out of order speculative reads, the reads would have
to be invalidated if *any* memory accesses by *any* processor were observed on
the system bus before any prior reads completed.  Which means that as soon
as you went from single processor to multi-processor you would see a
significant degradation in performance which would get worse the more
processors you added.  More processors, more memory bus activity.

This being the case, I don't think anyone at Intel would find themselves bound to
an unofficial memory model from the 90's when the official one would yield
significantly better performance.

And AMD clearly doesn't either.  Go read *their* architecture manuals.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.