Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Aug 29 2005 11:53 am


David Hopwood wrote:
[...]
> Stores by each processor occur in program order, that's clear. You're saying
> that stores made by processor 1 can nevertheless be loaded by processor 2
> out of program order. I see that there could be memory models and
> implementations for which this is possible, e.g. due to speculation.
> But how is it consistent with saying that all loads have acquire semantics?

http://groups.google.de/group/comp.arch/msg/c363731d2680ba8e

> 
> Example. Start with x == y == 0.
> 
> Processor 1:
>    a) x := 1
>    b) y := 1
> 
> Processor 2:
>    c) i := y
>    d) j := x
> 
> For a processor ordering model in which loads have acquire semantics,
> {i == 1, j == 0} is not possible. If the effects of speculation can be
> visible and need to be inhibited by an lfence between c) and d), then

For not weakened "ordinary" memory, the effects are not visible unless 
you sit on the "system bus" or care about discards.

> this outcome is possible. Which is it for IA-32?

{i == 1, j == 0} is not possible (for not weakened "ordinary" memory).

> 
> (And if anyone knows, which for AMD64 and EM64T?)

{i == 1, j == 0} is not possible (for not weakened "ordinary" memory).

[...]
> Which is all fine, but if speculative loads have no effect on the memory
> model, I still have no idea what the point of lfence is. Unless it is only
> needed when the memory ordering is weakened using MTRRs etc.?

That too.

http://groups.google.de/group/comp.programming.threads/msg/8d27f54bd4e85814

regards,
alexander.

.