Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Alexander Terekhov
Date : Sun Aug 28 2005 07:07 pm


David Hopwood wrote:
[...]
> then what's the point of the lfence instruction? 

SSE* fences are meant to control out-of-order SSE* writes of strings 
(sfence/mfence) and disable speculation (to cache stuff in order) of 
loads (lfence/mfence). SSE* stuff and ordering observable on "system 
bus" aside for a moment, the x86 memory model (processor consistency) 
did't change since 486. See also Intel Itanium Architecture Software 
Developer's Manual 6.3.4: "IA-32 instructions are mapped into the 
Itanium memory ordering model as follows...".

regards,
alexander.

.