Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Sun Aug 28 2005 08:45 am

Alexander Terekhov wrote:
> Joe Seigh wrote:
> [...]
> 
>>just trying to save Intel from themselves.  It's not a
>>correctness of implementation issue, it's a performance
> 
> 
> Under x86 memory model, all loads (including dependent ones) behave 
> in-order with respect to preceding loads. Processor can perform out-
> of-order speculative loads but they never yield incorrect results 
> (processor detects memory ordering violations and rolls back). 
> 

The official memory model states otherwise so you probably shouldn't
use the term "memory model" that way.  You mean load ordering as
implemented.  It's not clear whether you're talking about processor
order or memory order here.  If the latter it seems like a lot of
exotic bus snooping with an expensive performance hit just to enforce
a memory model which is not even the official one.  Seems even more strange
since they clearly and explicitly state exceptions to store order
for performance reasons.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.