Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : David Hopwood
Date : Sun Aug 28 2005 12:39 am

Alexander Terekhov wrote:
> David Hopwood wrote:
> [...]
> 
>>                      Intel and AMD's documentation clearly do *not*
>>guarantee anything about dependent loads.

On re-reading the docs, scratch "clearly" :-)

> Because they guarantee (albeit in a somewhat confusing language) 
> processor consistency model with classic "full" acquire for loads.
> 
> http://groups.google.de/group/comp.lang.c++.moderated/msg/40e6f068496500a7

I don't see it. If it is true that:

# Under x86 memory model, all loads (including dependent ones) behave
# in-order with respect to preceding loads. Processor can perform out-
# of-order speculative loads but they never yield incorrect results
# (processor detects memory ordering violations and rolls back).

and also that

# In a multiprocessor system, the following rules apply:
# * Individual processors obey the same rules as in a single
#   processor system.
# * Writes by a single processor are observed in the same
#   order by all other processors.
# [...]

then what's the point of the lfence instruction? Presumably it isn't just
a no-op? An example of an ordering that is prevented by adding an lfence
might help me to understand this.

Incidentally, are we talking about just 32-bit x86 here, or also AMD64/EM64T?

-- 
David Hopwood <david.nospam.hopwood@blueyonder.co.uk>

.