Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Sat Aug 27 2005 04:40 pm

David Hopwood wrote:
> Joe Seigh wrote:
>>
>> I'm trying to avoid being blindsided by Intel/AMD who seem to have almost
>> no awareness of what's going on in synchronization.
> 
> 
> Hey, that's not fair. Intel and AMD's documentation clearly do *not*
> guarantee anything about dependent loads. If it breaks, tough. This is
> no different from any other implementation-defined behaviour. I see no
> reason why Intel or AMD should be constrained to continue to support
> every random property of their current processor models that some bunch
> of hackers might rely on without any justification from the docs.
> 

The Linux kernel developers are a bunch of hackers? :)
Actually, no one is relying on it to work.  That's what
the wrapper macros are for.  They let you add a membar if
the implementation dependent stuff breaks.  But it would be ironic
if Intel inadvertently breaks the very stuff people are
using to make multi-core processors more scalable.  We're
just trying to save Intel from themselves.  It's not a
correctness of implementation issue, it's a performance
of implementation issue.


-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.