Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Peter Dimov
Date : Fri Aug 26 2005 01:51 pm

Alexander Terekhov wrote:
> Scott Meyers wrote:
>
> [... busted CacheComputedValue()/FetchComputedValue() example ...]
>
>    atomic<int> iValue;
>    atomic<BOOL> fValueHasBeenComputed(FALSE);
>    int ComputeValue();
>    // http://tinyurl.com/68jav
>    #pragma isolated_call(ComputeValue)
>
>    void CacheComputedValue()
>    {
>      if (!fValueHasBeenComputed.load(msync::naked_competing))
>      {
>        iValue.store(ComputeValue(), msync::naked_competing);

iValue doesn't seem to need atomicity... but that's not my point today.

>        fValueHasBeenComputed.store(TRUE, msync::ssb);
>      }
>    }
>
>    BOOL FetchComputedValue(int *piResult)
>    {
>      if (fValueHasBeenComputed.load(msync::cchlb_true))
>      {
>        *piResult = iValue.load(msync::naked_competing);
>        return TRUE;
>      }
>      else
>        return FALSE;
>    }
>
> To Peter: I've extended cc* stuff with path specific variants so
> that you can give compiler a hint on which path you don't really
> need isync.

This doesn't stand a chance, but something along those lines:

     if( fValueHasBeenComputed.load(msync::ccacq) )
     {
       ccacq_barrier();
       *piResult = iValue.load(msync::naked_competing);
       return TRUE;
     }
     else
       return FALSE;

is perfectly implementable. load/ccacq will map to either load/acq or
load/none, and ccacq_barrier() will map to no-op or #loadLoad/isync,
respectively.

.