Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Thu Aug 25 2005 06:52 pm

Peter Dimov wrote:
> Alexander Terekhov wrote:
> 
>>Peter Dimov wrote:
>>[...]
>>
>>>Can you give approximate PPC translation for the expression
>>>
>>>fValueHasBeenComputed.load(msync::cchlb_true)
>>>
>>>assuming that the compiler is not smart/atomics-aware and can't just
>>>insert the isync after the 'if'? (IOW, it can't analyze and optimize
>>>the 'load' in context... a library implementation, for example.)
>>
>>  lwz r4,0(r3) #load shared data
>>  cmpw r4,r4 #set CR0 to "equal"
>>  bne- $-8 #branch never taken
>>---
>>
>>and just add isync after "branch never taken".
> 
> 
> That's what I thought. In this case there is no difference between
> cchlb_true and cchlb (and ccacq, and even plain acq because of the fake
> control dependency.)
> 

You're not entirely sure what Alexander is talking about either?
As far as I can tell from his comments about ordering not being
enough is that he thinks the memory ops have to complete in
some cases which is not true as far as I know.  Usually you only
need those kind of memory barriers for putting boundaries on hardware
errors which can be imprecise and you want to ensure the error gets
reported in the right place.  E.g. process switching and IPC.
For normal synchronization you don't need it because there is
no error isolation between threads.

-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.