Subj : Re: Memory visibility and MS Interlocked instructions
To   : comp.programming.threads
From : Joe Seigh
Date : Thu Aug 25 2005 05:31 pm

Alexander Terekhov wrote:
> Joe Seigh wrote:
> [...]
> 
>>Yes on the first part.  
> 
> 
> No on the first part to the extent that "... thread W (the writer) 
> writes a value to variable x and thread R (the reader) later reads 
> the value of x ...  to guarantee that R sees the value written by 
> W, W must follow the write with a release membar and R must 
> precede the read with an acquire membar" is not true on shared 
> memory MP hardware level where acquire and release merely ensure 
> ordering with respect to other accesses.
> 

There's some conditional logic involved and possibly some atomicity
involved.  Are you merely quibbling or are you claiming there are
membars with no observable effect?

-- 
Joe Seigh

When you get lemons, you make lemonade.
When you get hardware, you make software.

.