Subj : implementing atomic<> on x86
To   : comp.programming.threads
From : Sean Kelly
Date : Thu Jul 28 2005 01:39 pm

I've been playing with implementing atomic<> in D on x86 architecture.
Most functions seem pretty straightforward--the msync::none versions
are all implemented in plain old code, synchronized store used LOCK
XCHG, and synchronized attempt_update uses LOCK CMPXCHG (all functions
are wrapped in a volatile block just to be safe).  That leaves
synchronized load.  Is there any reason to do some dummy operation just
so I can assert a LOCK, or is a synch operation even necessary on IA-32
in this case?  I've seen references (in the Itanium 2 manuals if I
remember correctly) which imply that reads/writes always occur in
program order on IA-32 machines, but I hesitate to believe this.
Basically, I'm wondering whether I need to do anything fancy when
implementing atomic<>::load(msync::acq) for x86.


Sean

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