Subj : Re: questions re: atomic<>
To   : comp.programming.threads
From : Chris Friesen
Date : Fri Jun 24 2005 04:29 pm

Sean Kelly wrote:
> As a matter of academic interest though, could you mention an
> architecture in common use that doesn't follow x86-like cache coherency
> rules?  I would think that even distributed systems would take steps to
> ensure data changes were propagated appropriately, though doing so may
> be a very expensive operation.

PPC has different rules about coherency.  I think inter-cpu stuff is 
different, but I know the software must manually ensure coherency 
between the dcache and icache, and unlike x86 it will issue out-of-order 
writes.

ARM doesn't even guarantee cache coherency within a single cpu--if 
you've got the same physical memory mapped at two different virtual 
addresses, you need to either flush the cache yourself or make that 
memory non-cacheable.

Chris

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