Subj : Re: questions re: atomic<>
To   : comp.programming.threads
From : Sean Kelly
Date : Fri Jun 24 2005 03:07 pm

Chris Friesen wrote:
> Sean Kelly wrote:
>
> > So then LOCK exists as one of the few instructions that forces a bus
> > lock, and this is actually to allow atomic CAS--the mfence aspect is
> > just a side effect.  This all makes a lot more sense now.  Thanks!
>
> Just a suggestion not totally related to this topic;
>
> You might want to be careful you don't code yourself into a total
> dependency on specific behaviours of current x86 chips, unless that's
> part of your design from the beginning.
>
> There are lots of other processors with different memory coherency rules.

That's why I phrased my questions in terms of atomic<>, as I assume
that any algorith written with respect to it should work fairly
universally, even if the implementation of each function differs from
architecture to architecture.

As a matter of academic interest though, could you mention an
architecture in common use that doesn't follow x86-like cache coherency
rules?  I would think that even distributed systems would take steps to
ensure data changes were propagated appropriately, though doing so may
be a very expensive operation.


Sean

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