Subj : Re: Hazard Pointers w/o memory barrier. To : comp.programming.threads From : Joe Seigh Date : Tue May 03 2005 08:13 pm On Mon, 02 May 2005 20:35:29 -0400, Joe Seigh wrote: > Finally getting around to modifying my current RCU > implementation to see how fast this will run. Just > taking the memory barriers out gave a 3x improvement > in read access throughput. At that rate that can be > considered as effectively zero overhead. About a 3x > slowdown in write access but that's because I don't > have the SMR logic in yet plus I have to stay with a > slightly crippled version of RCU to avoid imperial > entanglement. Adding the SMR logic should give me a > dramatic improvement in write throughput. Hmm... signals thrash things up quite a bit. Things slow way down unless I put the polling interval up to 300 msec to spread the signaling out a bit. Then I get about 1,286,000 reads/sec/thread for RCU+SMR vs. 176,000 reads/sec/thread for RCU with the same polling interval. It's a little over 700 reads/sec/thread for mutexes or rwlocks. Messing with signals doesn't look like it's worth the trouble especially given the scheduler artifacts from signaling differ from platform to platform. Looks like it will have to be platform specific code and no common reference implementation. If it got done hypothetically speaking. -- Joe Seigh When you get lemons, you make lemonade. When you get hardware, you make software. .