Subj : Re: SMR hazard pointers w/o memory barrier
To   : comp.programming.threads
From : Chris Thomasson
Date : Thu Apr 14 2005 06:44 am

> can be a lot more light-weight than DWCAS based atomic_ptr ( depends on 
> SMR "node" allocation scheme ).

(x86 specific)
Seems to be a "LOCK prefix /w cmpxchg8b is expensive " issue; SMR i686 only 
needs mfence...

.