Subj : SMR hazard pointers w/o memory barrier
To   : comp.programming.threads
From : Joe Seigh
Date : Wed Apr 13 2005 10:50 pm

I think it could be done.  Whether it should be done
is another question.

The hazard ptr load is only about 3x slower than a raw
ptr load which is a lot faster than with a membar in
there.  Assuming I put the volatile in the right place
and got a volatile ptr and not a ptr to volatile.
(No, volatile isn't the trick.  I'm just using it to
keep the timing loop from optimizing.)

It's on my list, right after lock-free AVL trees and
a bunch of other stuff.

-- 
Joe Seigh

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