Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : Michael Pryhodko
Date : Fri Apr 01 2005 06:43 pm

> > Ok. Situation:
> > - two processors have empy store buffers
> > - two processor were executing similar code for some time (i.e.
> > pipeline state should be similar)
> > - now they execute:
> > mov mem_addr, value
> > sfence
>
> > For me it is quite logical that they should spend the same amount
of
> > clocks  for this operation (suppose that flushing store buffer
takes
> > the same time  regardless of mem_addr). I understand that this is
only
> > my assumptions.
>
>     That's an absurd assumption and in general will not be true. This
is
> *especially* true if they're running similar code because they're
contending
> for resources and each time one CPU will win and one will lose
(cachewise).

Prove that this is absurd! So far to my understanding of x86 processor
internals (i.e. pipeline, retirement unit and so on) this should be
true.


>     There are so many reasons why this won't be true in the real
world and
> new ones are appearing all the time. What about interrupts?

if interrupt happens before mov -- everything is ok
if interrupt happens between mov and sfence -- it will flush store
buffer (see IA Manual) -- i.e. will do the same thing as sfence

so interrupt is ok here -- either store operation never begun, or it
begun and finished in the finite time

Bye.
Sincerely yours, Michael.

.