Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : Michael Pryhodko
Date : Fri Apr 01 2005 03:51 pm

> What microcode? The Intel arch manuals have some pseudocode
> listings, but no microcode AFAICS. The pseudocode says nothing
> about timing, and cycle counts should be taken as approximations.

ok, PSEUDOCODE. You right. I do not make any assumptions about cmpxchg
timing, I know that cycle counts are only approximations -- I have
spent much time reading IA Manuals. Here is my assumption:

under some similar circumstances (all processors store buffers are
drained) one processor could safely wait for other processors to finish
their "cmpxchg+sfence" code by executing the same instructions
(cmpxchg+sfence) on different memory location. If you can prove that
this wrong -- you are more than welcome, if not -- back off.

Bye.
Sincerely yours, Michael.

.