Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : Michael Pryhodko
Date : Fri Apr 01 2005 07:04 am

> My understanding is the processors locks the cach line with the LOCK
> prefix.  There's no way for other processors to observe that store.

Who told you that I am using LOCK prefix? Run this test app yourself!

> > About what I am trying to do -- see my answer to another posting.
>
> You mean this?
> ++ I am trying to "delay" one processor until others will finish
"write
> ++ and flush store buffers" with "write to another memory location"
(all
> ++ memory locations are cached).
>
> What you probably want is a barrier synchronization object.  See the
> pthread barrier documentation for more details.

No, this is a lock oriented only for x86. It could be easily adapted
for any other platfrom if it could provide necessary guarantees:
- compare-and-exchnage instruction
- OS can interrupt only between instructions
- full store (i.e. store+sfence on x86) timing is predictable
- every processor runs at the same speed and can not be delayed/stopped
- cache coherency mechanism is present

Well, read another posting for more detailed explanation.

Bye.
Sincerely yours, Michael.

.