Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : Joe Seigh
Date : Fri Apr 01 2005 09:57 am

On 1 Apr 2005 06:32:25 -0800, Michael Pryhodko <mpryhodko@westpac.com.au> wrote:

>> The redundant store isn't observable.  cmpxchg is atomic.  If there's
>> a problem, it's with your code elsewhere.  I'm not quite sure what
>> you are trying to do, so I don't know where to look or what
> suggestions
>> to make.
>
> Hmmm... try to run this small test app, you'll that:
> - cmpxchg (without LOCK prefix) is not atomic (it is impossible to do
> read+write operation atomic on x86 without using bus LOCK)
> - this stupid redundant store is quite observable, and basically it
> prevent my LOCK'less lock from working! It makes 'unlock' operation
> impossible to implement
>
> or on other hand I did a VERY stupid mistake...

My understanding is the processors locks the cach line with the LOCK
prefix.  There's no way for other processors to observe that store.
>
>
> About what I am trying to do -- see my answer to another posting.
>

You mean this?
++ I am trying to "delay" one processor until others will finish "write
++ and flush store buffers" with "write to another memory location" (all
++ memory locations are cached).

What you probably want is a barrier synchronization object.  See the
pthread barrier documentation for more details.

-- 
Joe Seigh

.