Subj : Re: CMPXCHG timing To : comp.programming.threads From : Joe Seigh Date : Fri Apr 01 2005 08:12 am On 31 Mar 2005 22:04:25 -0800, Michael Pryhodko wrote: > [implementation with problem skipped] > > So far it looks like speaking to myself. :) Well, it seems I found why > proposed code does not work. It seems that internal implementation of > CMPXCHG does not conform microcode listed in Intel Architecture manual, > i.e.: > processor reads value from memory, compares it with EAX and if they are > different processor WRITES BACK original value!! Shit!! Who and why > decided to do that??? Until someone explains me reasons behind this > decision I will consider it as very "bright" and "brilliant" move from > Intel. > > Proof: if you replace unlock function with: > (snip) > > test app starts working. But as far as I understand this implementation > is wrong -- i.e. it could put 0 into m_lock more than one time possibly > causing simultaneous entries thus violating lock guarantee (if we have > more than 2 competing threads). :( > > The redundant store isn't observable. cmpxchg is atomic. If there's a problem, it's with your code elsewhere. I'm not quite sure what you are trying to do, so I don't know where to look or what suggestions to make. -- Joe Seigh .