Subj : Re: CMPXCHG timing
To   : comp.programming.threads
From : Joe Seigh
Date : Fri Apr 01 2005 08:06 am

On 31 Mar 2005 17:38:46 -0800, Michael Pryhodko <mpryhodko@westpac.com.au> wrote:

> Well, I have decided to show my child :) It somewhat raw but readable:
>
(snip)

>
> unlock()
> {
>     // sanity check
>     ASSERT(A == P);
>
You need the sfence here for release semantics.  Strictly speaking
it has to be mfence (store/store + store/load)

>     // mark flag 'free'
>     A = 0;
>
>     // if OS will interrupt here this will drain store buffers
>     // (i.e. it will do the same as 'sfence' call below)
>
>     // make it visible to other threads
>     // we could skip this instruction but it will speed up lock release
>     // thus increasing overall performance in high-contention case
>     sfence
Um, no.  Memory barriers doesn't make memory visiblity faster for coherent
cache memory.  The opposite actually.

> }
>
>

I'm not sure why you're concerned with timings.  The membars don't do
what you think they do.  And if you try to force specific timing
behavior you are going to slow things down considerably which is
probably not what you want.

What are you trying to do here?


-- 
Joe Seigh

.