Subj : [x86] CMPXCHG timing
To   : comp.programming.threads
From : Michael Pryhodko
Date : Wed Mar 30 2005 10:45 pm

I understand that this question is quite platform-specific and can be
considered offtopic here, but...

suppose situation:
1. x86 platform (i.e. P6, Xeon and so on)
2. there are two different memory locations M1 and M2
3. M1 cached in processor P1 cache
4. M2 cached in processor P2 cache (P2 is second processor)
5. M1 = 0 and M2 = 0

CMPXCHG &M1, 0, 1
CMPXCHG &M2, 0, 1

Can it be safely assumed that execution time for instruction above will
be the same? (considering that first instruction will be executed on
P1, second -- on P2)


Also


Can it be safely assumed that execution time of:

// store buffers are empty
mov aligned_mem_addr, value_32bit
sfence // to flush store buffers

does NOT depends on aligned_mem_addr value? Any 'memory bank', 'DIMM
module' issues?

Bye.
Sincerely yours, Michael.

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