Subj : Re: CAS question
To   : comp.programming.threads
From : David Schwartz
Date : Fri Mar 25 2005 08:29 pm


"Toby Douglass" <toby.douglass@youknowwhattodo.summerblue.net> wrote in 
message news:MPG.1caea154fca8aef098a195@news-east.giganews.com...

> Is this true in all cases, though?  I don't know x86, but I could
> imagine that something simple like an addition or subtraction could be
> performed in situ on an operand to the atomic instruction.  In a
> hardware sense, it would just be a case of getting a ALU to perform an
> operation on an operand as it passes down the pipeline, which seems
> reasonable.

    The question is not whether is happens to be atomic or not but whether 
it's *guaranteed* to be atomic or not. It's not guaranteed to be atomic, so 
it would be an error to use it in a situation where the operation *had* to 
be atomic.

    The practical answer on x86 is that it will probably be atomic for most 
optimization settings because the atomic operation is the fastest. If, 
however, the code is complex enough and re-uses the value, it will not be 
atomic because then the atomic operation would be slower.

    Note, however, that an atomic operation in this sense is *NOT* atomic 
with respect to other processors! It is atomic in the sense that it's a 
single instruction and an interrupt can't occur between the read, the 
increment, and the writeback. Nothing stops the cache line from ping-ponging 
to another CPU during the operation even if the operation is a single 
instruction!

    This is not a speculative fetch, so it won't be pegged to the cache 
line.

    DS

.