Subj : load-after-store reordering for x86 wrt smr...
To   : comp.programming.threads
From : SenderX
Date : Mon Mar 14 2005 05:30 pm

Do you think that the store fence is needed in line 8:


/*
AC_SYS_APIEXPORT ac_i686_node_t* AC_CDECL
np_ac_i686_lfgc_smr_stack_mpmc_pop_dwcas
( ac_i686_stack_mpmc_t*,
  ac_i686_lfgc_smr_hazard_t );
*/
..align 16
..globl _np_ac_i686_lfgc_smr_stack_pop_dwcas
_np_ac_i686_lfgc_smr_stack_pop_dwcas:

1:  pushl %esi
2:  pushl %ebx

    _np_ac_i686_lfgc_smr_stack_pop_dwcas_reload:
3:  movl 12(%esp), %esi
4:  movl 4(%esi), %edx
5:  movl (%esi), %eax

    _np_ac_i686_lfgc_smr_stack_pop_dwcas_retry:
6:  movl 16(%esp), %ebx
7:  movl %eax, (%ebx) # store into hazard
8:  sfence # load-after-store prevention
9:  cmpl (%esi), %eax # load and compare hazard
10: jne _np_ac_i686_lfgc_smr_stack_pop_dwcas_reload
11: test %eax, %eax
12: je _np_ac_i686_lfgc_smr_stack_pop_dwcas_fail
13: movl (%eax), %ebx
14: leal 1(%edx), %ecx
15: lock cmpxchg8b (%esi)
16: jne _np_ac_i686_lfgc_smr_stack_pop_dwcas_retry

    _np_ac_i686_lfgc_smr_stack_pop_dwcas_fail:
17: movl 16(%esp), %esi
18: movl $0, %ebx
19: movl %ebx, (%esi)
21: popl %ebx
22: popl %esi
23: ret


Line 7 would be the first store, line 9 would be the load-after-store from 
another location condition. It seems that smr requires explicit barriers on 
x86 to prevent the algorithm from crashing...

.