Subj : Re: AMD has cmpxchg16b now - sort of To : comp.programming.threads From : David Hopwood Date : Wed Mar 09 2005 04:14 am Joe Seigh wrote: > On 08 Mar 2005 09:22:43 -0500, Nathan J. Williams wrote: > >> There has to be some way to tell whether the feature exists on a >> processor when code is running on it. Your choices are an option bit >> or a lookup table. The lookup table is going to be unmaintainable, so >> an option bit is clearly the way to go > > No I meant versioning. When they add a new architectural feature, > it becomes present on every processor of a certain version or later. > That way, all you need to know when getting a processor is the version > number. Using a feature bit doesn't preclude specifying that the feature bit must be set on all processors above a given version. In practice that is the usual policy, even if it isn't written down: it's almost unheard of for manufacturers to remove features once they have been added to a given processor line. >> Option bits are a pretty well entrenched mechanism for this on several >> architectures (not, notably, PowerPC, where you have to have a lookup >> table based on the CPU ID to find out if you have an FPU, AltiVec, or >> whatnot). >> > The synchronization stuff for powerpc was pretty well in place from the > very beginning. You don't have to query processor features to know > if load reserved and store conditional is installed. When they do add > stuff it is usually in a backwards compatible way. Powerpc isync just > executes as sync on processors without isync. Nitpick: that's forward compatibility. -- David Hopwood .