Subj : Re: AMD has cmpxchg16b now - sort of To : comp.programming.threads From : Joe Seigh Date : Tue Mar 08 2005 10:34 am On 08 Mar 2005 09:22:43 -0500, Nathan J. Williams wrote: > > [this seems more like a comp.arch topic than a c.p.t topic, but here > it is...] > > "Joe Seigh" writes: > >> Although they introduced the new features midstream, making it an option >> probably wasn't the best way to go. > > There has to be some way to tell whether the feature exists on a > processor when code is running on it. Your choices are an option bit > or a lookup table. The lookup table is going to be unmaintainable, so > an option bit is clearly the way to go No I meant versioning. When they add a new architectural feature, it becomes present on every processor of a certain version or later. That way, all you need to know when getting a processor is the version number. > >> That conbined with no external documentation on what processor >> models have what features makes it impossible to determine if the >> processor has the feature before buying it. > > Is that a serious problem? For a large-scale buyer (say, building a > compute cluster where this feature will be critical), you do an > evaluation where you can test it. For an individual who wants to mess > around with atomic operations, take advantage of return policies, > third-party reviews, and the like. It's a serious problem. Most places don't allow returns now, even in the case of defective product. You have to return to the OEM. The feature in question is a bit esoteric for review sites. > >> They probably should have gone with a architectural version numbering >> scheme that let you know at what point features become committed to the >> architecture. > > Option bits are a pretty well entrenched mechanism for this on several > architectures (not, notably, PowerPC, where you have to have a lookup > table based on the CPU ID to find out if you have an FPU, AltiVec, or > whatnot). > The synchronization stuff for powerpc was pretty well in place from the very beginning. You don't have to query processor features to know if load reserved and store conditional is installed. When they do add stuff it is usually in a backwards compatible way. Powerpc isync just executes as sync on processors without isync. Intel has and continues to add stuff in after the fact. You have this problem with almost every synchronization primative there is on Intel architectures. Look at the memory barrier instructions. You want those inline as calling an external function would be too expensive. But that makes them statically linked in effect, so you go with the lowest common implementation, an interlocked instruction to be on the safe side. -- Joe Seigh .