Subj : Re: sync vs. eieio on powerpc
To   : comp.programming.threads
From : Alexander Terekhov
Date : Tue Mar 01 2005 12:04 pm


Joe Seigh wrote:
[...]
> I'm guessing isync is "load/load" and "load/store".

I think that in sparc terms, it is more proper to view it as 
store/load and store/store in conjunction with successful store 
conditional.

<Forward Inline>

-------- Original Message --------
Message-ID: <4223610B.161294E@web.de>
Newsgroups: comp.std.c++
Subject: Re: C++ multithreading model
References: ... <1109297280.965767.203960@g14g2000cwa.googlegroups.com>

Michael Pryhodko wrote:
[...]
> By the way -- thank you for reading suggestion. WRL-95-9.pdf turned out

Note that some HW models as presented in that decade old piece are a 
bit outdated and not accurately reflect the current state (for example
Power[PC]).

[...]
> 'acquire/release' inside of RCpc region, 'sync' inside of 'PowerPC'

Well, see

http://www.google.de/groups?selm=4215E150.1856EF9A%40web.de

---
    while (!m_lock_status.store_conditional(new, msync)) {
*****
On assembly level (in MP-safe mode), acquire is implemented using 
trailing isync and release is implemented using leading sync/lwsync
instructions.
*****
---

For assembly details, see for example this illustration:

http://sources.redhat.com/ml/libc-alpha/2003-05/msg00095.html
(use of __ARCH_ACQ_INSTR and __ARCH_REL_INSTR)

regards,
alexander.

.