Subj : Re: Memory Barriers, Compiler Optimizations, etc.
To   : comp.programming.threads
From : Alexander Terekhov
Date : Mon Feb 07 2005 12:13 pm


"Neill Clift [MSFT]" wrote:
[...]
> I have seen you complain about the spinlock unlock
> routine that uses a volatile store. 

If your volatiles have Java-post-JSR-133-like "release+" semantics 
for writes (note: totally unneeded for standard C/C++ semantics -- 
sig_atomic_t statics for async signals and auto locals for jumps), 
then you don't need that idiotic "WithoutFence". If your volatiles 
don't have Java-post-JSR-133-like "release+" semantics for writes, 
then that "WithoutFence" thing won't help (on Itanic MP). 

[... InterlockedCompareExchange ...]

> You also suggested we don't do the right thing on
> the alpha. 

I suggested you post the code. Still waiting.

> I believe we do have a full barrier 

I believe that barrier makes little sense in the case of 
comparison failure.

regards,
alexander.

.