Subj : Re: Three membar-related questions To : comp.programming.threads From : David Schwartz Date : Fri Feb 04 2005 10:41 am "Joseph Seigh" wrote in message news:opsloqh7m5bs6ffg@grunion... >> On x86 processors up to P4, barriers are available, but not >> necessary. Intel has warned that this will change in the future. > I know stores are in order but I've heard some say the loads are also but > yes Intel has warned on that and unless you want to write code that > queries > the processor model, you should assume that. Though there's probably so > much code that assumes total store order that Intel would be taking a huge > risk making stores out of order. Loads are not in order, but processor magic makes things work as if they were in order. However Intel has made it completely clear that this magic may go away on a future processor, however it seems unlikely. The magic works like this -- if a speculative read is done, that read is pegged to the cache line. If the cache line is invalidated, so is the speculative read. So the net effect is that a read can occur out-of-order, but if another processor (or external device) attempts to modify the data after it was read, the speculative read will be ignored and a new read will be done. DS .