Subj : Three membar-related questions
To   : comp.programming.threads
From : Scott Meyers
Date : Fri Feb 04 2005 09:47 am

There are three issues I'm still unclear about:

  - Some things I read claim that memory barriers are applicable only to
    multiprocessor systems, because uniprocessor systems always appear to
    execute in program order.  Other things I read claim that this is
    untrue, that uniprocessors with pipelines and speculative fetches can
    run into memory visibility problems, too, so memory visibility is an
    issue even for uniprocessor programming.  Which is it?

  - What's the situation wrt multicore processors?  From a memory
    visibility point of view, are they multiprocessors (and hence in need
    of memory barriers in their software) or uniprocessors (and, assuming
    uniprocessors don't need memory barriers, not in need of them)?

  - I wrote up the following summary of the situation wrt memory barriers
    on x86, but I'm not sure it's true.  I'd appreciate comments on whether
    this is accurate:

      On x86 processors up to P4, barriers are available, but not
      necessary.  Intel has warned that this will change in the future.

Thanks for all clarifications,

Scott

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