Subj : Re: Memory Barriers, Compiler Optimizations, etc.
To   : comp.programming.threads
From : Alexander Terekhov
Date : Wed Feb 02 2005 01:39 pm


SenderX wrote:
[...]
> ac_cpu_i686_mb_store_ssb PROC
>  mov ecx, [esp + 4]
>  mov eax, [esp + 8]
>  sfence
>  mov [ecx], eax
>  ret
> ac_cpu_i686_mb_store_ssb ENDP

Compiler reordering aside for a moment, ordinary cpu_i686's stores 
have release semantics (ssb+slb). sfense (nop.ssb+hsb) is not needed. 
And, BTW, ordinary cpu_i686's loads have "full" acquire semantics 
(hsb+hlb).

regards,
alexander.

.