Subj : clocks vs. bus cycles
To   : Robin Sheppard
From : Jasen Betts
Date : Sun Oct 21 2001 11:04 pm

Hi Robin.

21-Oct-01 02:25:36, Robin Sheppard wrote to Jasen Betts


 JB>> if you're doing them repeateldy with REP MOVS you don't need to
 JB>> fetch the op-codes for each loop, but if you're using a JNZ to
 JB>> loop back you lose the pre-fetch cache and ther CPU has to fetch
 JB>> the instructions again (from the CPU cache, but it does cost)

 RS> Don't the different parts of the CPU execute in parallel?

yes, but a conditional jmp cancels that (AFAIK), and clears the prefetch

 RS> If so,
 RS> wouldn't this be masked by the time necessary to access RAM for
 RS> the actual memory operands of the instruction?  In short, wouldn't
 RS> MOVS still be slower?

it shouldn't be theoretically, it mainly depends what the chip designers
put the most priority on. One half of the CPU could handle the registers
while the other half handles the memory...

 RS>> I understand that SRAM would be faster than DRAM because you'd
 RS>> never run into a case where the CPU had to wait on RAM refresh,
 RS>> but what's the deal with "tagging for associative access"?  I
 RS>> thought memory locations were simply "associated" with their
 RS>> addresses.

 JB>> it's just a way of caching the most popular parts or mrmory...

 RS> Yes, but why would off-CPU caching make any difference,
 RS> besides the fact that the cache RAM is faster?

I don't think it would.

 -=> Bye <=-

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