Subj : clocks vs. bus cycles
To   : Jasen Betts
From : Robin Sheppard
Date : Sat Oct 20 2001 07:25 pm

 JB> if you're doing them repeateldy with REP MOVS you don't need to fetch
 JB> the op-codes for each loop, but if you're using a JNZ to loop back you
 JB> lose the pre-fetch cache and ther CPU has to fetch the instructions
 JB> again (from the CPU cache, but it does cost)

Don't the different parts of the CPU execute in parallel?  If so, 
wouldn't this be masked by the time necessary to access RAM for the 
actual memory operands of the instruction?  In short, wouldn't MOVS 
still be slower?

 RS> I understand that SRAM would be faster than DRAM because you'd
 RS> never run into a case where the CPU had to wait on RAM refresh,
 RS> but what's the deal with "tagging for associative access"?  I
 RS> thought memory locations were simply "associated" with their
 RS> addresses.

 JB> it's just a way of caching the most popular parts or mrmory...

Yes, but why would off-CPU caching make any difference, besides the 
fact that the cache RAM is faster?  In other words, if I had a machine 
that used SRAM instead of DRAM, for the main memory, why would an 
off-CPU cache have any benefit at all?

.... Apathy Error: Don't bother striking any key.

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